1. Field of the Invention
The present invention relates generally to transistors, and, more particularly to a GaN transistor with reduced output capacitance.
2. Description of the Related Art
Conventional transistor devices generally experience some level of transistor power dissipation due to conduction loss and switching loss. When transistors operate at higher frequencies, it becomes even more important to reduce switching loss. Additionally, in hard switching circuits, charging and discharging the output capacitor in every switch cycle influences the power dissipation of the transistor device.
Output capacitance (“Coss”) is the summation of gate-drain capacitance and source-drain capacitance. FIG. 1 schematically illustrates the Coss vs. drain-source voltage curve of a conventional GaN transistor as a dashed line.
FIG. 2(a) depicts a cross-sectional view of a conventional GaN transistor 101 when the drain-source voltage is at 0 volts. As shown, the GaN transistor 101 includes a substrate 109, buffer layers 110 formed on the substrate 109, and a two dimensional electron gas (“2DEG”) formed just below a barrier layer 104. Furthermore, the GaN transistor 101 includes a source electrode 102, a gate electrode 103, a drain electrode 105, a field plate 106 and a dielectric film 107.
In operation, when the drain-source voltage is at 0 volts, the Coss components of the GaN transistor 101 include a capacitor (“C1”) between the gate 103 and the drain side 2DEG 111, a capacitor (“C2”) between the field plate 106 and the drain side 2DEG 111, and a capacitor (“C3”) between the substrate 109 and the drain side 2DEG 111. When the drain-source voltage is at 0 volts, the capacitors C1, C2, and C3 are at their highest values.
FIG. 2(b) depicts a cross-sectional view of the conventional GaN transistor 101 when the drain-source voltage is a high voltage. As drain-source voltages increase, the drain side 2DEG 111 depletes toward the drain contact 105; C1 and C2 approach zero; and C3 decreases.
A primary objective of this invention is to reduce the output capacitance Coss of a transistor while maintaining gate width, which effectively reduces power dissipation, and, therefore, increases frequency capability in RF amplifiers that include such transistors.